Providing ESD protection for LED chips is well-known and commonplace. LEDs, especially gallium nitride-based LEDs, are particularly susceptible to damage with a reverse bias voltage across its anode and cathode. ESD voltages in normal environments can exceed 10,000 volts.
One example of a way to provide ESD protection for an LED chip is illustrated in FIGS. 1–3, which are described in U.S. Pat. No. 6,547,249, issued to the present inventor and others. This patent is incorporated herein by reference. FIG. 1 illustrates two diodes formed on the same semiconductor chip connected in an anti-parallel configuration. LED 10 is forward biased in normal operation and emits light. Upon a reverse bias voltage being applied to the terminals of LED 10, the ESD protection diode 12 conducts so as to shunt current away from LED 10 and clamp the reverse bias voltage across LED 10 to the voltage drop across diode 12.
FIGS. 2 and 3 are a top-down view and a cross-sectional view, respectively, of one embodiment 40 of a monolithic ESD protection circuit described in the '249 patent.
Diode structures A and B are formed on a highly resistive substrate 20. One structure A is connected as an LED to produce light, while the other structure B is used to clamp reverse breakdown in LED A. P-type layers 41a and 41b overlay active regions 49a and 49b, which are formed on n-type layers 42a and 42b. A trench 43 is formed between devices A and B. Ledges for contact formation on n-type layers 42a and 42b are exposed such that the n-electrodes 45a and 45b are on opposite sides of trench 43. A dielectric layer 47 electrically insulates the metallization layer 46a from all electrical contact except where openings are made for interlayer interconnects, or for contacts to such areas as the p-contacts or n-contacts. P-electrode 44a and n-electrode 45b are connected by interconnect 46a such that the p-contact of LED A is connected to the n-contact of clamping device B. In the region where interconnect 46a is deposited, the n-contact of LED A is isolated from interconnect 46a by dielectric layer 47. As shown in FIG. 2., the interconnection between the p-contact of LED A and the n-contact of clamping device B is formed on one side of the device, and the interconnection between the n-contact of LED A and the p-contact of clamping device B is formed on the other side of the device. The structure can then be connected to a submount or other structure (not shown) by solder bumps or wire bonds 48.
One drawback associated with placing an ESD diode on the same chip as an LED intended to emit light is that the ESD diode uses up area on the chip, thus reducing the area and the light output of the light producing diode. Although the ESD diode may output light when forward biased, such light output is inconsequential to its ESD function. Another problem is that the high currents through the forward biased ESD diode must be carried through the series resistance of the diode. The series resistance includes the resistances of the metal and the bulk resistances of the N and P type material forming the ESD diode. The series resistance becomes very significant at high ESD currents since a relatively high voltage (V=IRs) may be dropped across the series resistance. Additionally, the structures of FIGS. 1–3 do not allow the light emitting diode and ESD diode to be individually tested for quality and reliability since the interconnections are already made on the chip.